Deutsche Version dieser Seite
Next:Instruction Fetch Unit and Instruction Window  Up:Structural and functional Description  Previous:Structural and functional Description  Contents

Bus/Memory Interface Unit

This unit represents the interface of the processor core to its environment. It manages communications to external memory and ISA bus. The testing equipment contains more external interfaces that can be freely connected but are not used in this design.

The arrangement of such an interface unit between pipeline and environment is advantageous: Independant of the interface the design of the pipeline can take place in its environment, and when this environment changes, the only work to be done is updating one unit - the interface unit. This makes use of the pipeline easier in different environments, the design can be reused easily.

Memory or bus access are started independantly from the instruction fetch unit (section 4.4.2) as well as the execution unit (section 4.4.4). This is why there exist structural conflicts. The Bus/Memory Interface Unit prevents fetch and execution units from using external bus structure at the same time. Additionally it drives other outputs like the two LED of the testboard.

For an implementation without delays caused by wait cycles operands for use in the execution unit have to be read out of external memory by a higher priority. Data flow of the pipeline is not dependant on write access to external memory (as long as there is no overflow on the stack which causes data to be stored into external memory by a "dribbler" [7], which is not planned to be implemented in this prototype). It still is a kind of work on operands so that it runs with medium priority. Fetching instructions from memory is defined the lowest priority of all memory accesses. The reason for this is the instruction window (see section 4.4.2), which will normally hold enough data to decode (with 32 Bit fetch bandwidth about 2 Bytecode instruction being read from memory each fetch cycle). Resulting is the following priority list:

1.
memory read from execution unit
2.
memory write from execution unit
3.
memory read from fetch unit
The execution unit can only start one memory access at a time (read or write). Therefore the internal address busses (pcadr, memadr) will be multiplexed onto the external address bus AEX and data read or written to data bus DEX,respectively. Which type of access is defined by control bus CEX.

Additionally the interface unit can communicate with the ISA bus of a personal computer. This is how different test programs are written into the external memory of the testboard, and results stored in this memory can be read out for observation purposes.

The statechart in figure 4.14 shows the functionality of the Bus/Memory Interface Unit: In concurrent processes data from memory or bus is processed as well as clock division done so that memory or stack access can be executed in one pipeline clock cycle.



Figure 4.14: Statechart of Bus/Memory Interface Unit



Next:Instruction Fetch Unit and Instruction Window  Up:Structural and functional Description  Previous:Structural and functional Description  Contents
Robert Zulauf

2000-04-27